1. Field of the Invention
The present invention relates to an integrated circuit (IC) chip having on-chip capacitors formed in its metal layers, and particularly relates to using such capacitors in connection with routing power and ground to portions of the circuit that require high transient peak power.
2. Description of the Related Art
Today""s IC chips require more power than in the past. At the same time, operating frequencies also have significantly increased, thus significantly shortening cycling times. As a result of these developments, it is often necessary to have available a power supply that is capable of delivering high peak power to different portions of the circuit. Unfortunately, the wire resistance between the power and ground input terminals of the IC, on the one hand, and the specific portion of the circuitry to which such power and ground is being delivered, on the other, often severely limits the peak power that can be delivered to that portion of the circuit.
One possible solution to this problem is to attempt to place those portions of the circuitry that require relatively high peak power close to the power and ground input terminals. In a standard IC, this requires placing those portions of the circuitry close to the periphery of the IC and, more specifically, close to the power and ground terminals on the periphery. Unfortunately, such space is limited. Thus, when there are many different portions of the circuitry that require high peak power, this solution often is unacceptable.
A related solution is to use a flip-chip IC package. In a flip-chip package, the input/output (I/O) terminals for the chip are located across the entire surface of the chip, rather than just at the periphery. As a result, by including multiple power and ground terminals dispersed across the surface of the IC, the routing distance between the power and ground input terminals and the desired portion of the circuitry often can be significantly shortened. Unfortunately, flip-chip fabrication usually is more expensive than standard chip fabrication. Therefore, this solution also has limited applicability.
Thus, what has been long needed is a technique for delivering high peak power to portions of a circuit where it is needed that can be implemented in a standard IC chip package.
The present invention addresses the foregoing need by utilizing unused portions of the chip""s metal layers to form capacitors that can function as power cells.
Thus, in one aspect the invention is directed to supplying power and ground to locations on an integrated circuit (IC) device that has multiple metal layers for routing wires and a substrate for forming electronic components. Initially, the technique according to this aspect of the invention identifies an overlap area where two of the multiple metal layers that are adjacent to each other have open space. It is noted that this overlapping open space may have occurred by happenstance or may have been intentionally designed into the chip during the routing phase of the IC design so as to occur near a portion of the circuit that requires high peak power. A plate is then formed in the overlap area of each of the two metal layers so as to construct a capacitor. Generally, the plates of the capacitor are formed so as to occupy substantially all of the overlap area. Then, one plate of the capacitor is connected to power, the other plate of the capacitor is connected to ground, and the plates of the capacitor are also connected to locations on the substrate of the IC device.
By forming a capacitor in an IC""s metal layers in the foregoing manner, the present invention often can supply more transient peak power to a portion of the circuit than would have been possible with conventional designs. Moreover, because it is common to have a significant amount of unused space in an IC""s metal layers, such a capacitor often can be included at little additional cost. By including multiple such capacitors, the present invention often can fully accommodate the transient peak power requirements of each portion of the IC, again without significant additional cost.
In a further aspect, the invention is directed to an integrated circuit (IC) device that includes a semiconductor substrate on which electronic components are formed and multiple metal layers on which wires are routed. Formed on the multiple metal layers is a capacitor that includes a first plate formed on a first metal layer and a second plate formed on a second metal layer that is adjacent to the first metal layer. According to this aspect of the invention, an area in which the first plate and the second plate overlap has a width of at least twice the width of a typical wire on the IC device.
This configuration can permit capacitors of 10 femtofarads or more to be included within the IC, at little additional cost. By utilizing such capacitors as power cells (e.g., by connecting one plate to power and the other to ground and then connecting both to an area of the substrate where high transient peak power is required), this configuration can frequently deliver much higher transient peak power than conventional designs would permit.
The foregoing summary is intended merely to provide a brief description of the general nature of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.